1. Field of the Invention
The present invention relates to a high speed bus circuit system for transferring data with low power dissipation and at high speed in digital devices such as computers.
2. Description of the Related Art
In digital devices such as computers, it is necessary to connect interconnect data lines of various integrated circuits (hereafter referred to as ICs) including a processor with a bus and exchange data. However, the signal rate on the bus is finite. In high speed data transfer, therefore, signal propagation time cannot be disregarded. If there is a mismatching place of transfer impedance on the bus, waveform distortion caused by reflection makes high speed data transfer difficult. Thus a high speed bus reduced as far as possible in transfer impedance is needed.
FIG. 11 is a diagram showing the configuration of a conventional high speed bus circuit system described in, for example, "Comparison of small amplitude interfaces of bus systems headed for 100 MHz age, "Nikkei Electronics, No. 93. 9. 27.
In conventional high speed bus circuit systems, a scheme in which terminal resistors are pulled up to power supplies on both ends of a bus as shown in FIG. 11 is often used. In such a scheme, the terminal resistors function to reduce the reflection distortion, and consequently high speed data transfer can be conducted.
In FIG. 11, characters IC1 through IC5 denote integrated circuits each incorporating a driver (D) and a receiver (R). Characters SL1 through SL4 denote transmission lines mounted on print circuit boards to transfer signals. Characters Ra and Rb denote terminal resistors connected to ends of the bus. Remaining ends of the resistors Ra and Rb are connected to the power supplies.
Operation will now be described by referring to FIGS. 11 and 12. FIG. 12 is a diagram illustrating the operation of the conventional high speed circuit system.
In FIG. 11, data transfer operation via the high speed bus is conducted in such a manner that one of the IC1 through IC5 connected to the bus drives the bus and a signal appearing on the bus is received by other ICs. For example, in the case where the IC3 drives the bus and transmits data, the IC1, IC2, IC4 and IC5 receive that data.
For example, it is now assumed that the IC3 drives the bus. First of all, portions of the transmission lines SL2 and SL3 located in the vicinity of the IC3 are simultaneously driven. In the leftward direction, the signal is transferred from the transmission line SL2 to the SL1, then to the terminal resistor Ra as represented by a broken line in FIG. 11. In the rightward direction, the signal is transferred from the transmission line SL3 to the SL4, then to the terminal resistor Rb.
The terminal resistors Ra and Rb function to absorb the mismatching of transfer impedance caused in the IC1 and IC5 portions. When the terminal resistance value has coincided with the impedance of the transmission line, the most significant effect is obtained.
Assuming now that the terminal resistors Ra and Rb are not present and the configuration excepting the Ra and Rb is the same as that of FIG. 11, FIG. 12 is a schematic diagram showing how the signal propagates with arrows together with schematic waveforms at respective time points. In FIG. 12, the ordinate indicates the time and the abscissa indicates the position.
In the case where the terminal resistors Ra and Rb are not present, the transfer impedance in the signal transfer direction becomes infinitely great (i.e., the transmiss ion line becomes open). In these positions, therefore, significant reflection is caused and reflected components are returned on the bus while following the routes indicated by arrows on broken lines. As shown in FIG. 12, large reflection is caused in each of the positions of the IC1 and IC5, and reflected components are transferred to respective ICs and appear as waveform distortions. if such waveform distortion is large, data errors are caused by the distortion and consequently the high speed data transfer cannot be conducted.
On the other hand, in the case where the terminal resistors Ra and Rb are connected in the positions of the IC1 and IC5, respectively, resistance values of the terminal resistors become the transfer impedance values in the signal transfer direct ion and the reflected components (i.e. , the components indicated by the broken line arrows in FIG. 12) are suppressed. This reflected component becomes "0" when the transmission ling coincides with the terminal resistance value. By connecting terminal resistors, therefore, the waveform distortion is improved and high speed transfer becomes possible.
In the foregoing description, it is supposed that input impedance values of the IC1, IC2, IC3, IC4 and IC5 functioning as the receivers R are sufficiently high and exert little influence on the signal transfer and consequently the waveform distortion caused by them can be disregarded.
Since the conventional high speed bus circuit system is configured as heretofore described, high speed signals can be transferred. However, the conventional high speed bus circuit system has problems of a temperature rise and quickened battery exhaustion caused by great useless DC (direct current) power dissipation in the terminal resistors located at both ends of the bus.
For example, assuming that each of the terminal resistors Ra and Rb has a resistance value of 50 ohms (.OMEGA.), the power supply voltage is 5 V, and the data is "L", the useless DC power dissipation W per signal line of the bus becomes
W=2.times.5.sup.2 /50=1 watt. PA1 W.sub.64 =1.times.64=64 watts.
If the bus is formed by 64 signal lines, the useless DC power dissipation W.sub.64 amounts to